Systolic Array MNIST Accelerator

4×4 weight-stationary · INT8 · cycle-accurate twin of the SystemVerilog RTL
cycle 0 state — layer — tile — block —

Input · draw a digit or pick one

RTL Prediction

·
draw or pick a digit, then run

Network Progress

L0 · 784→32—
L1 · 32→16—
L2 · 16→10—

Processing-Element Array — activations flow →, partial sums flow ↓

activation partial sum stationary weight drain → accumulator